Thin wafer detectors with improved radiation damage and crosstalk characteristics

ABSTRACT

The present invention provides for reduced radiation damage susceptibility, decreased affects of crosstalk, and increased flexibility in application. In one embodiment, the present invention includes a back side illuminated photodiode array with a back side etching that minimizes the active area layer, thereby decreasing the affects of crosstalk. The back side etching is preferably, but by no way of limitation, in the form of “U” or “V” shaped grooves. The back side illuminated with back side etching (BSL-BE) photodiodes are implemented in an array and have superior performance characteristics, including less radiation damage due to a thinner active area, and less crosstalk due to shorter distances for minority carriers to diffuse to the PN junction.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This invention relies on, for priority, U.S. Provisional Application 60/468,181, having a priority date of May 5, 2003, entitled “DETECTORS WITH IMPROVED RADIATION DAMAGE AND CROSSTALK CHARACTERISTICS”.

FIELD OF THE INVENTION

[0002] The present invention pertains generally to the field of radiation detectors, and in particular, relates to radiation detectors manufactured with thinner wafers, thereby yielding reduced crosstalk between detecting regions and decreased susceptibility to radiation damage, having front surface contacts.

BACKGROUND OF THE INVENTION

[0003] Arrays of photosensitive diodes are used in an assortment of applications including, but not limited to, radiation detection, optical position encoding, and low light-level imaging, such as night photography, nuclear medical imaging, photon medical imaging, multi-slice computer tomography (CT) imaging, and ballistic photon detection etc. Typically, photodiode arrays may be formed as one- or two-dimensional arrays of aligned photodiodes, or, for optical shaft encoders, a circular or semicircular arrangement of diodes.

[0004] One problem with detection devices is that they are susceptible to various radiation damage mechanisms, such as displacement damage resulting in total dose effects and ionization damage resulting in bulk effects. Both these mechanisms adversely affect the performance of detectors, transistors and integrated circuits.

[0005] Certain detector characteristics that are most affected include detector leakage current, doping characteristics, charge collection, and carrier lifetime. Over time, detectors show an increased reverse-bias current and increased forward voltage drop due to radiation damage. Further, a change in doping level, due to radiation damage, adversely affects the width of the depletion region, i.e. the voltage required for full depletion and a decrease in carrier lifetime results in signal loss as carriers recombine while traversing the depletion region.

[0006] Another disadvantage with conventional detection devices is the amount and extent of crosstalk that occurs between adjacent detector structures, primarily as a result of minority carrier leakage current between diodes. The problem of crosstalk between diodes becomes even more acute as the size of the detector arrays, the size of individual detectors, the spatial resolution, and spacing of the diodes is reduced.

[0007] In certain applications, it is desirable to produce optical detectors having small lateral dimensions and spaced closely together. For example in certain medical applications, it would beneficial to increase the optical resolution of a detector array in order to permit for improved image scans, such as computer tomography scans. However, at conventional doping levels utilized for diode arrays of this type, the diffusion length of minority carriers generated by photon interaction in the semiconductor is in the range of at least many tens of microns, and such minority carriers have the potential to affect signals at diodes away from the region at which the minority carriers were generated. Therefore, the spatial resolution obtainable may be limited by diffusion of the carriers within the semiconductor itself, even if other components of the optical system are optimized and scattered light is reduced.

[0008] Various approaches have been used to minimize such crosstalk including, but not limited to, providing inactive photodiodes to balance the leakage current, as described in U.S. Pat. Nos. 4,904,861 and 4,998,013 to Epstein et al., the utilization of suction diodes for the removal of the slow diffusion currents to reduce the settling time of detectors to acceptable levels, as described in U.S. Pat. No. 5,408,122, and providing a gradient in doping density in the epitaxial layer, as described in U.S. Pat. No. 5,430,321 to Effelsberg.

[0009] Despite attempts to improve the overall performance characteristics of photodiode arrays and their individual diode units, within detection systems, photodiode arrays capable of reducing crosstalk while being less susceptible to radiation damage are still needed. Additionally, there is need for a semiconductor circuit and an economically feasible design and fabrication method so that it is capable of improving the spatial resolution of detectors integrated therein.

SUMMARY OF THE INVENTION

[0010] The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. In one embodiment, the present invention comprises a back side illuminated photodiode array with a back side etching that minimizes the active area layer, thereby decreasing the affects of crosstalk. The back side etching is preferably, but by no way of limitation, in the form of “U” or “V” shaped grooves. The back side illuminated with back side etching (BSL-BE) photodiodes are implemented in an array and have superior performance characteristics, including less radiation damage due to a thinner active area, and less crosstalk due to shorter distances for minority carriers to diffuse to the PN junction. The present invention also comprises a front side illuminated photodiode, with contact pads on the front side, further comprising isolation trenches, resulting in zero cross talk.

[0011] In one embodiment, the photodiode array comprises a substrate having at least a front side and a back side, photodiodes integrally formed in the substrate forming the array, and metal contacts provided on the front side. The fabrication of the array involves diffusing a n+ layer on the back side of the substrate, forming a deep n+ region; applying a first masking layer on the back side; applying a second masking layer on the back side; applying a photoresist mask on the back side, forming an etching pattern; using the etching pattern to etch the first masking layer, the second masking layer; removing the photoresist mask; etching the deep n+ region, and the substrate; and finally coating the back side of the substrate with an antireflective coating.

[0012] Preferably, the array substrate is made of n doped silicon. The deep n+ region and shallow n+ region may be of varied doping concentration. In addition, it is preferred that the first masking layer and the second masking layer are SiO₂, Si₃N₄, or any other similar suitable material. It is also preferred that the grooves formed in the substrate are “V”-shaped grooves. It is also preferred that the first masking layer, second masking layer, and antireflective coating form a three-layer dielectric membrane, which further forms a bridge between the grooves in the back side of the device wafer.

[0013] Optionally, the preferred embodiment of the present invention may comprise a handle wafer bonded to the front side of the device wafer, for improved strength and manageability. Front surface cathode and anode contacts are brought to the surface of the handle wafer via metallization of channels, formed from the side walls of the handle wafer.

[0014] In one embodiment, the fabrication of the photodiode array involves applying a first masking layer on the back side of the device wafer; applying a second masking layer on the back side; applying a photoresist mask on the back side, forming an etching pattern; etching the second masking layer according to the photoresist mask pattern; etching the first masking layer according to the photoresist mask pattern; removing the photoresist mask; etching the substrate, thus forming grooves in the substrate; diffusing a shallow n+ layer onto the back side of the substrate, forming a shallow n+ region; and finally, coating the back side of the substrate with an antireflective coating.

[0015] In another embodiment, the manufacture of the photodiode array of the present invention comprises applying a first masking layer on the back side; applying a photoresist mask on the back side, forming an etching pattern; etching the first masking layer according to the photoresist mask pattern; removing the photoresist mask; etching the substrate, forming grooves in said substrate; diffusing a n+ layer onto the back side of the substrate, forming a shallow n+ region; and finally, coating the back side of said substrate with an antireflective coating.

[0016] In yet another embodiment, the photodiode array of the present invention may be fabricated via the following steps: diffusing a n+ layer on the back side of the substrate, forming a deep n+ region; applying a first masking layer on the back side; applying a second masking layer on the back side; applying a photoresist mask on the back side, forming an etching pattern; first etching the second masking layer according to the photoresist mask pattern; second etching the first masking layer according to the photoresist mask pattern; removing the photoresist mask; third etching the deep n+ region and substrate, forming grooves in the substrate; diffusing a n+ layer onto the back side of the substrate, forming a shallow n+ region; and finally, coating the back side of the substrate with an antireflective coating.

[0017] In yet another embodiment of the present invention, the photodiode array comprises a substrate having at least a front side, a back side, and a handle wafer bonded to the front side, photodiodes integrally formed in the substrate forming the array; and a plurality of electrical contacts in electrical communication with said front side, wherein front surface cathode and anode contacts are brought to a top surface of said handle wafer via metallization of channels.

[0018] In another preferred embodiment of the present invention, the photodiode array comprises a substrate having at least a front side, a back side, and a handle wafer bonded to said front side, photodiodes integrally formed in the substrate forming the array, a buried oxide layer formed between the substrate and handle wafer, and a plurality of trenches operating as isolation trenches to nonconductively isolate electrically active regions. In this preferred embodiment, the photodiode array is front side illuminated and has back side contacts. The isolation trenches provide for zero cross talk.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other features and advantages of the present invention will be appreciated, as they become better understood by reference to the following detailed description when considered in connection with the accompanying drawings:

[0020]FIG. 1a is a cross sectional view of a preferred front side of one embodiment of a back side etched, front side contact photodiode array of the present invention;

[0021]FIG. 1b is a cross sectional view of one embodiment of a back side etched, front side contact photodiode array of the present invention, also illustrating a preferred front side of the present invention;

[0022]FIG. 2a is cross sectional view of a preferred embodiment of the back side of a back side etched, front side contact photodiode array of the present invention;

[0023]FIG. 2b is a cross sectional view of one embodiment of the back side of a back side etched, front side contact photodiode array of the present invention;

[0024]FIG. 3 depicts a back side illuminated, front side contact photodiode array of the present invention, further comprising a handle wafer, for improved strength and manageability;

[0025]FIG. 4a depicts a back side illuminated, front side contact photodiode array of the present invention, further comprising a handle wafer;

[0026]FIG. 4b depicts a back side illuminated, front side contact photodiode array of the present invention, further comprising a handle wafer; and

[0027]FIGS. 5a, 5 b, and 5 c depict different views of an array of photodiodes with a plurality of trenches functioning as isolation trenches, to non-conductively isolate electrically active regions from each other.

DESCRIPTION OF THE INVENTION

[0028] This application hereby incorporates by reference co-pending application, entitled “FRONT ILLUMINATED BACK SIDE CONTACT THIN WAFER DETECTORS”, which also relies on, for priority, U.S. Provisional Application 60/468,181, having a priority date of May 5, 2003, entitled “DETECTORS WITH IMPROVED RADIATION DAMAGE AND CROSSTALK CHARACTERISTICS”. The invention described therein comprises a plurality of front side illuminated photodiodes, optionally organized in the form of an array, with both the anode and cathode contact pads on the back side. The front side illuminated, back side contact (FSL-BSC) photodiodes have superior performance characteristics, including less radiation damage, less crosstalk using a suction diode, and reliance on reasonably thin wafers. The invention, as described therein, is a photodiode array having a substrate with at least a front side and a back side; a plurality of photodiodes integrally formed in the substrate forming the array wherein each photodiode has a middle layer juxtaposed between a front layer and a back layer; a plurality of electrical contacts in electrical communication with the back side; and suction diodes positioned at selected locations within the array, wherein the fabrication of said array involves a masking process comprising the steps of applying a first p+ mask on said front side and applying a second p+ mask on said back side.

[0029] The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. Various modifications to the preferred embodiment will be readily apparent to those of ordinary skill in the art, and the disclosure set forth herein may be applicable to other embodiments and applications without departing from the spirit and scope of the present invention and the claims hereto appended. Thus, the present invention is not intended to be limited to the embodiments described, but is to be accorded the broadest scope consistent with the disclosure set forth herein.

[0030] The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, and increased flexibility in application. In one embodiment, the present invention comprises a back side illuminated photodiode array with a back side etching that minimizes the active area layer, thereby decreasing the affects of crosstalk. The back side etching is preferably, but by no way of limitation, in the form of “U” or “V” shaped grooves. The back side illuminated with back side etching (BSL-BE) photodiodes are implemented in an array and have superior performance characteristics, including less radiation damage due to a thinner active area, and less crosstalk due to shorter distances for minority carriers to diffuse to the PN junction.

[0031] Referring now to FIGS. 1a, 1 b, 2 a, and 2 b, the active areas in the back side of the photodiode arrays are etched to minimize the likelihood of crosstalk while still providing the detector with sufficient strength to avoid easy breakage. FIGS. 1a, 1 b, 2 a, and 2 b depict exemplary photodiode arrays having a first region of maximum thickness, a second region of minimum thickness, and a third region of varying thickness which depends upon the level of back side etching. The “regions” are loosely defined areas of the photodiode arrays and are described herein to illustrate the teachings of the present invention. While these regions are present in the embodiments as described in the above-mentioned figures, the specifications regarding the number of regions and their corresponding thicknesses that comprise the photodiode array are merely illustrative of the present invention and not intended to be limiting.

[0032] The first region comprises p+ regions and n+ regions that are separated by a thin active layer, minimizing the degree of crosstalk between the diodes and reducing susceptibility to radiation damage. The second region comprises a shallow n+ region and, optionally, a deep n+ region, both doped with a suitable impurity of a similar conductivity type and located close to the back side of the wafer. The second region provides the photodiode area with increased strength and resistance to breakage. The third region forms the bottom surface wall (depth) of preferably “U” or “V” shaped grooves etched into the back side of the photodiode array and spans to the front side surface of the device wafer. Ideally, the total depth of the first region would equal the total depth of the second and third regions combined.

[0033] In the preferred embodiment, the back side illuminated photodiode arrays of the present invention have front side contacts. Referring now to FIG. 1a, a preferred embodiment of the front side of the photodiode arrays of the present invention is depicted. Metal contact pads are provided on the front and are in electrical communication with the anode and cathode surface structures. Both regions 150 a and 155 a are positioned directly below the front surface of the device wafer 105 a, sharing their top face with front surface of device wafer 105 a. Heavily doped regions 150 a and 155 a may be doped with a suitable impurity of a selected conductivity type, such as p-type or n-type. Regions 150 a and 155 a are doped with opposite impurities of selected conductivities. For example, but not limited to such example, if region 150 a is doped with a suitable impurity of selected conductivity that is p-type, then region 155 a is doped with n-type. In addition, a thin region of active layer separates regions 150 a and 155 a. The thin active layer minimizes the degree of cross talk between diodes and reduces susceptibility to radiation damage.

[0034] Referring again to FIG. 1a, cross section 105 a of one embodiment of photodiode array 100 a is shown. Photodiode array 100 a comprises regions, including first region 110 a, second region 115 a and third region 120 a, with maximum, minimum, and variable thicknesses, respectively. As an example, and by no way of limitation, the three regions may possess the following specifications: first region 110 a may have a thickness of approximately 125 μm, second region 115 a may have a thickness of approximately 50 μm, and third region 120 a may be of a varying thickness, ranging from a minimum of approximately 75 μm to a maximum of approximately 125 μm, depending on the level and pattern of etching. The above-mentioned specifications are only mentioned by way of illustration and are not binding. The specification can be easily changed to suit the design, fabrication, and functional requirements suggested herein.

[0035] First region 110 a comprises two heavily doped regions, 150 a and 155 a, as described above. First region 111 a is separated into two additional regions for ease of discussion—second region 115 a and third region 120 a. Second region 115 a, in a preferred embodiment, comprises shallow n+ regions 135 a and deep n+ regions 130 a, both doped with a suitable impurity of a similar conductivity type and located close to the back side of the wafer. Both shallow n+ regions 135 a and deep n+ regions 130 a may optionally be heavily doped with an impurity of similarly selected conductivity type, such as p-type or n-type. A large active area fills the depth created at the junction of both shallow n+ region 135 a and deep n+ region 130 a. For example, and by no way of limitation, shallow n+ region 135 a is preferably 0.3 μm in thickness and deep n+ region 130 a is preferably 2 μm in thickness. Second region 115 a provides the photodiode array with increased strength and resistance to breakage. Third region 120 a, in combination with second region 115 a, forms “U” or “V” shaped etchings in the back side of photodiode (depending on the type of etching used).

[0036] Referring now to FIG. 2a, a cross sectional view of a preferred embodiment of a single crystal semiconductor substrate or device wafer 201 a having a plurality of photodiodes positioned in an array 200 a therein is depicted. Note that the front side of photodiode array 200 a is as depicted and described above with reference to FIG. 1a. Device wafer 201 a comprises three regions, including first region 215 a, second region 220 a, and third region 230 a, with maximum, minimum, and variable thicknesses, respectively. Various constructional details with respect to the regions in photodiode array 200 a have been explained with reference to FIG. 1a above and will not be discussed here. General dimensions and relevant specifications, however, are discussed in the following paragraph and are by no way limiting to the design of this preferred embodiment of the present invention.

[0037] Referring back to FIG. 2a, first region 215 a is preferably of a thickness of approximately 125 μm and further comprises a p+ region and an n+ region, separated by a thin active layer just below the front side of device wafer 201 a. Second region 220 a preferably has a minimum thickness 50 μm and preferably comprises a shallow n+ region 202 a and a deep n+ region 203 a, both doped with a suitable impurity of a similar conductivity type. Shallow n+ region 202 a is preferably 0.3 μm in thickness and deep n+ region 203 a is preferably 2 μm in thickness—both located close to the back side of device wafer 201 a. Deep n+ region 203 a serves to reduce dark leakage current in the photodiode array.

[0038] Device wafer 201 a may be made up of various materials, and is preferably, but not limited to Si or Ge. The crystal orientation of wafer 201 a is preferably <1-0-0>. The back side of device wafer 201 a is selectively etched, at appropriate positions via a suitable etching technique to form three dimensional (hereinafter, “3-D”) microstructures therein, thus minimizing the active area layer and decreasing the affects of crosstalk. The grooves are preferably “U” or “V” shaped with a depth of approximately 50 μm from the back surface. The present invention may employ various other 3-D microstructures of varying shapes and dimensions including, but not limited to, grooves, pyramidal pits, pyramidal cavities etc. for minimizing active area layers. Such various other microstructures will be readily apparent to one of ordinary skill in the art having the benefit of this disclosure. The above specifications are not limiting with respect to the 3-D microstructures and their accompanying dimensions can be changed to suit any design, fabrication, and functional requirements.

[0039] For example, and by no way of limitation, a wet etching technique is used to form concave “V”-shaped grooves on the back side of device wafer 201 a, at suitable positions, such as positions 205 a, as shown in FIG. 2a. Via such wet etch technique, mono-crystalline wafers etch faster in certain crystallographic directions than in others, thereby allowing for certain layers or portions of the wafer to act as a “stop” for the etch process. This involves both a selection of appropriate wafer orientation and a suitable mask pattern for the photographic mask. Optionally, reactive ion etching (RIE) may be used to form concave grooves on the back side of device wafer 201 a. The grooves formed via this technique, however, form “U”-shaped grooves. The sidewalls of such grooves are more vertical, wherein the wall is angled at less than 10 degrees.

[0040] As shown in FIG. 2a, portions of the back side of photodiode array 200 a comprise three layers, forming dielectric membrane 255 a. Three-layer dielectric membrane 255 a forms a bridge between V-shaped grooves 235 a. First layer 270 a is comprised of SiO₂ and is preferably of a thickness of 4000 Å. Si₃N₄ comprises second layer 275 a and is preferably of a thickness of 2000 Å. Third layer 280 a of dielectric membrane 255 a is comprised of SiO₂, as an antireflective coating, and is preferably of a thickness of 900 Å. A person of ordinary skill would appreciate that the specifications and dimensions of the components of the dielectric membrane are not limited to the abovementioned specifications and can be easily adjusted to suit varied economical, technical or operational specifications.

[0041] “V”-shaped grooves 235 a etched into device wafer 201 a form bottoms 240 a, created at a depth 245 a of the “V”-shaped groove from the backside of device wafer 201 a. Sidewalls 250 a extend from bottom 240 a to the back side of device wafer 201 a, at an angle. Preferably, “V”-shaped grooves 235 a are of a depth of approximately 50 μm (depicted as 245 a) and are located at a distance of approximately 75 μm from the front side of wafer 201 a. A person of ordinary skill would appreciate that the specifications and dimensions of the “V”-shaped grooves etched into the wafer are not limited to the above-mentioned specifications and can be easily adjusted to suit varied economical, technical or operational specifications.

[0042] As a first manufacturing step, back side of device wafer 201 a is heavily doped via phosphorus diffusion or high dose implantation, followed by deep driving, thus obtaining a deep n+ doped region 203 a. Subsequent to the formation of the deep n+ doped region, back side of device wafer 201 a is first coated with first layer 270 a of a suitable masking material. Preferably, first masking layer 270 a is fabricated from a material such as SiO₂ and in a thickness of 4000 Å. Back side of device wafer 201 a is then coated with second layer 275 a, comprising Si₃N₄, and preferably of a thickness of 2000 Å. A person of ordinary skill in the art would appreciate that the utilization of materials for the fabrication of first and second masking layers are not limited to SiO₂ or Si₃N₄, and can easily be changed to suit other design or operational requirements.

[0043] Once first layer 270 a and second layer 275 a are applied to back side of device wafer 201 a, the back side is coated with a conventional photoresist mask, thus forming a window pattern on the back side of wafer 201 a. The photoresist mask is formed using any of the conventional photolithographic techniques including, but not limited to, optical, UV (i.e. ultraviolet), EUV (i.e. enhanced ultraviolet) photolithography, e-beam or ion-beam lithography, x-ray lithography, interference lithography, or any other similar technique. Second layer 275 a is then etched in accordance with the formed window pattern, using a dry etching (gas) process. First layer 270 a acts as a stop etch layer in the dry etch process, as the process passes through SiO₂ at a significantly slower rate than Si₃N₄. First layer 270 a is then etched according to the window pattern via the use of buffered HF₃, thereby exposing device wafer 201 a, coated with deep n+ regions 203 a through the pattern achieved via the use of the photoresist mask. The photoresist mask is then removed from the back side of the wafer, prior to etching the grooves in the substrate, as the wet etchant would damage the photoresist mask. As an alternative, the Si₃N₄ layer and pattern already formed in the previous steps functions as the etch mask.

[0044] “V”-shaped grooves are then etched into device wafer 201 a and deep n+ regions 203 a, through the use of a wet (chemical) etch process. It is preferable to use KOH in the chemical etch process of this step. It must be noted here that the etch rate of the silicon wafer is orientation dependent—the more slowly etched crystal planes form the side and end walls of the V-grooves. Device wafer 201 a is preferably a wafer having a crystal orientation <1-0-0>. V-shaped grooves etched parallel to the <1-1-0> direction have planar facets which bind the V-shaped grooves, lying in the <1-1-1> plane. The planar facets are inclined at an angle of 54.7° with respect to the <1-0-0> plane. The groove sizes are controlled by the corresponding mask windows, the accuracy of their alignment with the crystal axes, the erosion rate of the edges of the mask, and the relative etch rates of the crystal planes. Typically, the finished widths of V-grooves can be controlled to within 0.5 to 1 μm. Manufacturing methods of 3-D microstructures, such as concave cavities or grooves, of various shapes and textures in semiconductor substrates are well known in the art. Orientation selective wet etching techniques including, but not limited to, isotropic, anisotropic etching, etc. are preferred. Like other conventional etching techniques, orientation selective wet etching techniques also utilize custom-made or conventional mask patterns. Preferably, a “V”-shaped groove pattern, formed on a suitable photographic mask in accordance with the principles of the present invention, is used to protect one area of the wafer 201 a during the stripping and etching processes. The present invention, however, is directed towards providing preferred methods of masking and etching the active area, thereby used to minimize the likelihood of crosstalk while still providing the detector with sufficient strength to avoid easy breakage. The scope and spirit of the invention is no way limited, and other 3-D microstructures may be etched into the back side of wafers in accordance to the preferred properties of the present invention.

[0045] After “V”-shaped grooves are etched into the device wafer shallow n+ layer 202 a is diffused onto the back side of device wafer 201 a. The back side of device wafer 201 a, including the surface of V-shaped grooves 235 a, is then coated with layer 280 a, an antireflective coating. Various antireflective coating designs, such as 1 layer, 2 layer, 3 layer, and 4+layers may be employed. By way of example, and by no means limiting, the 1-layer antireflective coating design adopted herein utilizes thin film materials, such as oxides, sulfides, fluorides, nitrides, selenides, metals, among others. In a preferred embodiment of the present invention, layer 280 a comprises SiO₂ AR (i.e. silicon dioxide antireflective). Preferably, the SiO₂ AR layer has a thickness of 900 Å.

[0046] Referring now to FIG. 2b, the back side of another embodiment of the present invention is depicted. Note that the front side of photodiode array 200 b has already been described above with respect to FIG. 1a. Device wafer 201 b comprises three regions, including first region 215 b, second region 220 b, and third region 230 b, with maximum, minimum, and variable thicknesses, respectively. By way of comparison with FIG. 2a, FIG. 2b depicts a cross section of photodiode array 200 b without deep n+ region (shown as 203 a in FIG. 2a). Third region 230 b is of a varying thickness and in combination with second region 220 b, constitutes “U”-shaped or “V”-shaped etchings 235 b in the back side of wafer 201 b. Various constructional details with respect to the three regions in photodiode array 200 b have been explained with reference to FIGS. 1a and 2 a and will not be discussed here. It should be noted, however, that the first manufacturing step as described with respect to FIG. 2a is omitted in the manufacture of photodiode array 200 b due to the omission of the deep n+ region.

[0047] Now, referring back to FIG. 1a, the back side of yet another embodiment of the back side of the photodiode array of the present invention is depicted. Note that front side characteristics and optimal dimensions with respect to FIG. 1a have already been discussed above. Device wafer 105 a may be made up of various materials, and is preferably, but not limited to Si or Ge. The crystal orientation of wafer 105 a is preferably <1-0-0>. Back side of device wafer 105 a is selectively etched, at appropriate positions via a suitable etching technique to form three dimensional (hereinafter, “3-D”) microstructures therein, thus minimizing the active area layer and decreasing the affects of crosstalk. The grooves are preferably “U” or “V” shaped with a depth of approximately 50 μm from the back surface. The present invention may employ various other 3-D microstructures of varying shapes and dimensions including, but not limited to, grooves, pyramidal pits, pyramidal cavities etc. for minimizing active area layers. Such various other microstructures will be readily apparent to one of ordinary skill in the art having the benefit of this disclosure. The above specifications are not limiting with respect to the 3-D microstructures and their accompanying dimensions can be changed to suit any design, fabrication, and functional requirements.

[0048] For example, and by no way of limitation, a wet etching technique is used to form “V” shaped grooves on the back side of device wafer 105 a, at suitable positions, such as positions 125 a, as shown in FIG. 1a. Via such wet etch technique, monocrystalline wafers etch faster in certain crystallographic directions than in others, thereby allowing for certain portions of the wafer to act as a “stop” for the etch process. This involves both a selection of appropriate wafer orientation and a suitable mask pattern for the photographic mask. Optionally, reactive ion etching (RIE) may be used to form concave grooves on the back side of device wafer 105 a. The grooves formed via this technique, however, form “U”-shaped grooves. The sidewalls of such grooves are more vertical, wherein the wall is angled at less than 10 degrees.

[0049] As a first manufacturing step, back side of device wafer 105 a is heavily doped via phosphorus diffusion or high dose implantation, followed by deep driving to obtain a deep n+ doped region 130 a. First layer 140 a, of a suitable masking material, is then thermally grown onto the back side of device wafer 105 a. Preferably, the first masking layer is fabricated from a material such as SiO₂ and in a thickness of 4700 Å. Back side of device wafer 105 a is then coated with second layer 165 a, comprising deposited Si₃N₄, and preferably of a thickness of 2000 Å. A person of ordinary skill in the art would appreciate that the utilization of materials for the fabrication of first and second masking layers are not limited to SiO₂ or Si₃N₄, and can easily be changed to suit other requirements.

[0050] Once first layer 140 a and second layer 165 a are applied to back side of device wafer 105 a, the back side is coated with a conventional photoresist mask, thus forming a window etch pattern. The photoresist mask is formed using any of the conventional photolithographic techniques including, but not limited to, optical, UV (i.e. ultraviolet), EUV (i.e. enhanced ultraviolet) photolithography, e-beam or ion-beam lithography, x-ray lithography, interference lithography, or any other similar technique. Second layer 165 a is then etched in accordance with the formed window pattern, using a dry etching (gas) process. First layer 140 a acts as a stop etch layer in the dry etch process, as the process passes through SiO₂ at a significantly slower rate than Si₃N₄. First layer 140 a is then etched in the window pattern via the use of buffered HF₃, thereby exposing device wafer 105 a and deep n+ regions 130 a through the window pattern achieved via the use of the photoresist mask.

[0051] The photoresist mask is then removed from the back side of the wafer, prior to etching the grooves in the substrate, as the wet etchant would damage the photoresist mask. As an alternative, the Si₃N₄ layer and pattern already formed in the previous steps functions as the etch mask.

[0052] “V”-shaped grooves 170 a are then etched into device wafer 105 a, first removing doped n+ deep regions 130 a. After “V”-shaped grooves are etched into the device wafer shallow n+ layer 135 a is diffused onto the back side of device wafer 105 a, coating only the surface of V-shaped grooves 170 a. The surface of V-shaped grooves 170 a is then coated with layer 145 a, an antireflective coating. Various antireflective coating designs, such as 1 layer, 2 layer, 3 layer, and 4+layers may be employed. By way of example, and by no means limiting, the 1-layer antireflective coating design adopted herein utilizes thin film materials, such as oxides, sulfides, fluorides, nitrides, selenides, metals, among others. In a preferred embodiment of the present invention, layer 145 a comprises SiO₂ AR (i.e. silicon dioxide antireflective). Preferably, the SiO₂ AR layer has a thickness of 900 Å.

[0053] Referring now to FIG. 1b, a second preferred embodiment of a photodiode array 100 b is depicted. Photodiode array 100 b comprises first region 110 b, second region 115 b, and third region 120 b, preferred dimensional details of which are discussed above with reference to FIG. 1a. In addition, the doping materials used, masking layers formed, and etching techniques adopted to form the 3-D microstructures have already been explained above with reference to FIG. 1a. In the manufacture of photodiode array 10 b, however, only a single first masking layer is applied to the back side of the photodiode array. For example, and by no way of limitation, the single masking layer 165 b is preferably Si₃N₄ and of a thickness of 4000 Å. In addition, second region 115 b comprises only a shallow n+ region 135 b.

[0054] Referring to FIG. 3, another preferred embodiment of the photodiode array of the present invention is illustrated. The back side illuminated, front side contact (BSL-FSC) photodiodes are implemented in an array and have superior) performance characteristics, including low dark current (current leakage), very high shunt resistance, less crosstalk, and less radiation damage due to a thinner active area. To improve strength and manageability, the photodiode as shown in FIG. 3 further comprises a handle wafer. The front surface cathode and anode contacts are brought to the surface of the handle wafer through the metallization of channels connecting a p+ metal pad to the p+ region and an n+ metal pad to the n+ region. The starting material for photodiode array 300 is device wafer 301 with handle wafer 302 bonded to the front surface of device wafer 301.

[0055] Handle wafer 302 has channels 303 a, 303 b, and 303 c (hereinafter referred to collectively as “303”) formed in handle wafer 302 at three preferred positions, for example and by no means limiting, those marked “A”, “B”, and “C”. Starting precisely from the top surface of handle wafer 302, channels 303 extend through the total depth of handle wafer 302 to the front side of the device wafer 301. The side walls of the handle wafer 302 define channels 303. Handle wafer 302 is coated with a first layer 304 and a second layer 305, both forming top and sidewalls of handle wafer 302. First oxide insulation layer 304 coats the inner walls of channels 303. For example, but not limited to such example, SiO₂ may be used for the first oxide insulation layer 304. Second layer 305, layered on top of first layer 304, coats a major portion of the inner walls forming channels 303 and at least partially covering the top surface of handle wafer 302. Second layer 305, a heavily doped pad layer of a selected conductivity type, in conjunction with layer 304 coats inner walls which form channels 303. Preferably, second layer 305 is either p+ doped or n+ doped. Second layer 305 in channel 303 at area “B” uses a n+ doped pad wherein p+ doped pads are used at areas “A” and “C”.

[0056] Channels 303, having first layer 304 and second layer 305 coating side walls of handle wafer 302 and forming inner walls of channel 303, are vertically aligned with respect to layers 306, 308, and 309. Further second layer 305 (vertical p+ pad in this preferred embodiment) in channels 303 comprising areas “A” and “C” covers a large portion, preferably a substantial portion of the depth of channel 303 (or the portion that substantially forms the depth of handle wafer 302). Bottom layers 306 and 308 are in electrical communication with horizontal p+ pads 307 as depicted in the cross-sectional view of FIG. 3. In channel 303 comprising area “B”, horizontal n+ pad 307 is electrically connected to n+ region 309.

[0057] Areas between second layers 305 (either p+ or n+), running along the sidewalls of handle wafer 302 and forming channels 303, can be described as void areas “A”, “B”, and “C”. Due to metallization of channels 303 along the entire periphery of the vertical sidewall layer 305 and the horizontal pads 307 therein, the front surface cathode and anode contacts on device wafer 301 are brought to the surface of the handle wafer 302 with channels 303 connecting the p+ metal pads to the p+ regions and the n+ metal pads to the n+ regions.

[0058] The back side of device wafer 301, as shown in FIG. 3, has already been described in a preferred embodiment with respect to FIG. 2a. The description as offered in FIG. 2a is herein incorporated by reference.

[0059] Various other methods of physically separating active regions of photodiode arrays may be readily apparent to a person of ordinary skill in the art. It should be noted that the above description about separation of active regions of individual photodiodes, via formation of insulation layers there between, is merely for illustrative purposes and not intended to limit the applicability of the present invention.

[0060] Referring now to FIGS. 4a and 4 b, additional preferred embodiments of the back side illuminated-front side contact photodiode arrays are shown. The BSL-FSC photodiodes have thin active layers, thereby improving crosstalk characteristics and reducing susceptibility to radiation damage. A plurality of p+ and n+ regions are separated by a shallow active region. To improve strength and manageability, the photodiode further comprises a handle wafer. The front surface cathode and anode contacts are brought to the surface of the handle wafer through the metallization of channels connecting a p+ metal pad to the p+ region and an n+ metal pad to the n+ region.

[0061] Referring now to FIG. 4a, a cross sectional view of one embodiment of the present invention is shown. As an example, and by no way of limitation, silicon may be utilized in accordance with the principles of the present invention. The starting material for the BSL-FSC photodiode is a silicon wafer comprising a device wafer 401 a bonded to a handle wafer 402 a using a suitable bonding material via an appropriate method of bonding silicon wafers. Such bonding methods are well known to one of ordinary skill in the art. Both device wafer 401 a and handle wafer 402 a are preferably formed of the same semiconductor material of a selected conductivity type, such as p-type or n-type. The device wafer 401 a preferably has a thickness of approximately 50 μm.

[0062] Handle wafer 402 a increases strength in the BSL-FSC photodiode while improving manageability. The front surface cathode and anode contacts are brought to the top surface of the handle wafer 402 a through the metallization of channels 404 a connecting a p+ pad to the p+ region and a n+ pad to the n+ region. Channels 404 a, formed in handle wafer 402 a are marked with area designations “A”, “B”, and “C”. The inner side walls of handle wafer 402 forming channels 404 a comprise first layer 405 a, which is an oxide insulation layer and second layer 406 a, which is a contact layer for handle wafer 402 a. Material selection and manufacturing method for such layers have already been described with reference to FIG. 3 and will not be described in detail here.

[0063] As shown in FIG. 4a, boron doped polysilicon is preferably used as the material for second layer 406 a, and define defining channel areas “A” and “C”, in conjunction with first layer 405 a and bottom wall 407 a. A person of ordinary skill in the art would readily appreciate that the selection and utilization of material for the second sidewall layer is not limited to boron doped polysilicon and can be changed to suit varied technical and operational specifications. Second sidewall layer 406 a defining channel area “B” preferably comprises, but is not limited to phosphorus doped polysilicon.

[0064] Also depicted in FIG. 4a is a plurality of selected p+ and n+ doped regions separated from a substantially uniform shallow n+ layer 403 a by a thin active region. Portions of the thin active region or layer are also juxtaposed between the plurality of p+ and n+ regions. The shallow n+ layer 403 a improves the quantum efficiency at shorter wavelengths and reduces dark current (current leakage) of the photodiode.

[0065] Referring now to FIG. 4b, a cross sectional view 400 b of another preferred embodiment of the BSL-FSC photodiode is shown. The preferred specifications of the BSL-FSC photodiode are described above with respect to cross section 400 a of FIG. 4a. In contrast, however, FIG. 4b employs p+ metal pad layers and n+ metal pad layers as the sidewalls that define channels 401 b. FIG. 4b shows front surface cathode and anode contacts, brought to the surface of handle wafer 402 b through the metallization of channels 401 b connecting a p+ metal pad to the p+ region and an n+ metal pad to the n+ region.

[0066] In another embodiment, the present invention comprises a front side illuminated photodiode array with zero crosstalk due to dielectric isolation. The front side illuminated, zero crosstalk (BSL-ZC) photodiodes are implemented in an array and have superior performance characteristics, including less radiation damage due to a thinner active area and zero crosstalk due to a complete isolation of the carrier regions. FIGS. 5a, 5 b, and 5 c depict different views of an array of photodiodes with a plurality of trenches functioning as isolation trenches, to non-conductively isolate electrically active regions from each other.

[0067] Specifically, FIG. 5a depicts one such exemplary trench, functioning as an isolation trench. A device layer 515 is in physical communication with a trench defined by a doped trench sidewall 530, a trench sidewall liner 535, preferably an oxide, and polysilicon 540 as a filler. The trench is further defined by a polysilicon step 520, preferably having a height at or around 300 nm, and a TEOS trench endpoint 525, preferably having a height at or around 500 nm. In one embodiment, the trench has a width at or around 2.5 μm to 4 mu. In the above-mentioned embodiment, various specifications for device wafer thicknesses and trench widths are provided. The provided specifications are not limiting with respect to device wafer thicknesses and trench widths and their accompanying dimensions can be changed to suit any design, fabrication, and functional requirements.

[0068] Trench sidewall 530 is of n-type (phosphorous) doping, if the device layer material is also n-type. The doping type of the trench sidewall layer matches that of the device layer. Sheet resistance of the trench sidewall doping is less than 50 ohm per square. The trench sidewall liner thickness, for each sidewall, is 150 nm+/−35 nm. The polysilicon 540 filled trench isolated photodiode array 500 eliminates electrical migration between the adjacent detecting regions therein, thereby preventing minority carrier leakage current and achieving zero crosstalk characteristics.

[0069] Custom silicon-on-insulator (SOI) starting material for photodiode array 500 of the present invention is a device layer 515 with a buried layer 505 formed on top of a buried oxide (BOX) layer, resting on a handle wafer 503. Handle wafer 503 can be of any type as is well known to those of ordinary skill in the art, ranging from handle wafers of low resistivity to handle wafers of high resistivity. Additionally, low cost handle wafers may be employed. Also, handle wafers of optimal performance can be used. Handle wafer 503 is doped with an impurity of a selected conductivity type, either n-type or p-type and preferably has a thickness of approximately 300-700 μm.

[0070] Handle wafer 503 is oxidized, thereby forming a buried oxide layer surrounding the handle wafer. Device layer 515 is preferably a double-sided polished wafer (to improve bonding characteristics) and is subjected to shallow n+ diffusion or ion implantation, thereby forming layer 505 on the back side of device layer 515. The front side of handle wafer 503, covered with the oxide layer, is then bonded to the backside of device layer 515, which has an original thickness of 400 μm. The BOX layer is used for the bonding process.

[0071] Device layer 515 is preferably formed of the same semiconductor material as handle wafer 503 and is ground and polished to a preferred thickness of 20 μm. It is ground and polished to such desired thickness. Optionally, device layer 515 may be grown as an epitaxial layer on top of handle wafer 503. The positioning of the trenches is then formed using a standard photolithography step, as mentioned above, thereby obtaining a pattern on the thinned wafer. Using the photoresist pattern, a dry etching technique, such as reactive ion etching is then used to etch the silicon wafer for trench formation. The photoresist layer is removed following the step of silicon trench etching.

[0072] Trench sidewall 530 is deposited via, but not limited to, a thermal deposition technique. The sidewall oxide layer 535 is then formed along the vertical wall of the trench. The wafers are then subjected to polysilicon deposition, thereby filling the trenches with polysilicon. It is preferred that the trenches in this preferred embodiment of the present invention are filled after the growth of trench sidewall liner 535, so that the polysilicon 540 filler is more likely to be void free. In the final step, a TEOS oxide layer is deposited on the surface.

[0073] Referring now to FIGS. 5b and 5 c, an array of photodiodes affixed to a handle wafer 503 with a layer of buried oxide therebetween is shown. Note that photodiode array 500 is front side illuminated because the presence of the buried oxide layer will act as an impenetrable barrier to a light generated carrier. Each photodiode has surface n+ and surface p+ regions separated from a base n+ region by an active layer and are separated from adjacent photodiodes by a trench acting as an isolating layer. Spaced semiconductor regions 545 are formed in device layer 515 via standard semiconductor processing, masking and etching techniques, as are well known to those of ordinary skill in the art. A boundary between the device layer wafer 515 and each spaced region 545 defines a p-n junction (not shown).

[0074] Of particular advantage, the present invention provides a method for filling an isolation trench or other semiconductor structure whose active areas require a non-conductive material, typically but not limited to undoped SiO₂, to physically and non-conductively isolate said electrically active regions.

[0075] The above discussion is aimed towards providing a preferred embodiment incorporating the novel aspects of the present invention and it should be understood that the foregoing illustration is not the only application where the present invention can be reduced down to practice. The present invention can be suitably modified to incorporate other possible embodiments as well. The scope of the invention is defined solely by the accompanying claims and within the scope of the claims; the present invention can be employed in various other situations. For example, other device-to-device isolation, active are patterning, active area reduction, reduction of crosstalk, formation of electrical contacts via through holes, and reduction of radiation damage techniques could be employed while still staying within the scope of the present invention. 

What is claimed is:
 1. A photodiode array comprising: a substrate having at least a front side and a back side; a plurality of photodiodes integrally formed in the substrate forming said array; a plurality of metal contacts provided on said front side, wherein the fabrication of said array comprises: diffusing a n+ layer on said back side of said substrate forming a deep n+ region; applying a first masking layer on said back side; applying a second masking layer on said back side; applying a photoresist mask on said back side, forming an etching pattern; first etching said second masking layer according to said photoresist mask pattern; second etching said first masking layer according to said photoresist mask pattern; removing said photoresist mask; third etching said deep n+ region and said substrate, forming grooves in said substrate; diffusing a n+ layer onto said back side of said substrate, forming a shallow n+ region; and coating said back side of said substrate with an antireflective coating.
 2. The array of claim 1, wherein said substrate is made of n doped silicon.
 3. The array of claim 1, wherein said deep n+ region and said shallow n+ region may be of varied doping concentration.
 4. The array of claim 1, wherein said first masking layer and said second masking layer are SiO₂ or Si₃N₄.
 5. The array of claim 1, wherein said grooves formed in said substrate are “V”-shaped grooves, further formed by a bottom surface and angled sidewalls.
 6. The array of claim 1, wherein said first masking layer, said second masking layer, and said antireflective coating form a three-layer dielectric membrane.
 7. The dielectric membrane of claim 6, wherein said membrane forms a bridge between said grooves in said back side.
 8. The array of claim 1, wherein said antireflective coating layer is silicon dioxide.
 9. The array of claim 1, wherein a handle wafer is bonded to said front side.
 10. The array of claim 9, wherein front surface cathode and anode contacts are brought to a surface of said handle wafer via metallization of channels.
 11. The array of claim 10, wherein said channels are formed from side walls of said handle wafer.
 12. The array of claim 11, wherein said side walls forming said channels comprise a first layer and a second layer.
 13. The array of claim 12, wherein said first layer comprises an oxide insulation layer.
 14. The array of claim 12, wherein said second layer comprises a heavily doped pad layer of a selected conductivity type of either p+ doped or n+ doped.
 15. A photodiode array comprising: a substrate having at least a front side and a back side; a plurality of photodiodes integrally formed in the substrate forming said array; a plurality of metal contacts provided on said front side, wherein the fabrication of said array comprises: applying a first masking layer on said back side; applying a second masking layer on said back side; applying a photoresist mask on said back side, forming an etching pattern; first etching said second masking layer according to said photoresist mask pattern; second etching said first masking layer according to said photoresist mask pattern; removing said photoresist mask; third etching said substrate, forming grooves in said substrate; diffusing a shallow n+ layer onto said back side of said substrate, forming a shallow n+ region; and coating said back side of said substrate with an antireflective coating.
 16. The array of claim 15, wherein said substrate is made of n doped silicon.
 17. The array of claim 15, wherein said first masking layer and said second masking layer are SiO₂ or Si₃N₄.
 18. The array of claim 15, wherein said grooves formed in said substrate are “V”-shaped grooves, formed by a bottom surface and angled sidewalls.
 19. The array of claim 15, wherein said first masking layer, said second masking layer, and said antireflective coating form a three-layer dielectric membrane.
 20. The dielectric membrane of claim 20, wherein said membrane forms a bridge between said grooves in said back side.
 21. The array of claim 15, wherein said antireflective coating layer is silicon dioxide.
 22. A photodiode array comprising: a substrate having at least a front side and a back side; a plurality of photodiodes integrally formed in the substrate forming said array; a plurality of metal contacts provided on said front side, wherein the fabrication of said array comprises: applying a first masking layer on said back side; applying a photoresist mask on said back side, forming an etching pattern; first etching said first masking layer according to said photoresist mask pattern; second etching said substrate, forming grooves in said substrate; removing said photoresist mask; diffusing a n+ layer onto said back side of said substrate, forming a shallow n+ region; and coating said back side of said substrate with an antireflective coating.
 23. The array of claim 22, wherein said substrate is made of n doped silicon.
 24. The array of claim 22, wherein said first masking layer is SiO₂ or Si₃N₄.
 25. The array of claim 22, wherein said grooves formed in said substrate are “V”-shaped grooves, formed by a bottom surface and angled sidewalls.
 26. The array of claim 22, wherein said antireflective coating layer is silicon dioxide.
 27. A photodiode array comprising: a substrate having at least a front side and a back side; a plurality of photodiodes integrally formed in the substrate forming said array; a plurality of metal contacts provided on said front side, wherein the fabrication of said array comprises: diffusing a n+ layer on said back side of said substrate, forming a deep n+ region; applying a first masking layer on said back side; applying a second masking layer on said back side; applying a photoresist mask on said back side, forming an etching pattern; first etching said second masking layer according to said photoresist mask pattern; second etching said first masking layer according to said photoresist mask pattern; removing said photoresist mask; third etching said deep n+ region and substrate, forming grooves in said substrate; diffusing a n+ layer onto said back side of said substrate, forming a shallow n+ region; and coating said back side of said substrate with an antireflective coating.
 28. The array of claim 27, wherein said substrate is made of n doped silicon.
 29. The array of claim 27, wherein said deep n+ region and said shallow n+ region may be of varied doping concentration.
 30. The array of claim 27, wherein said first masking layer and said second masking layer are SiO₂ or Si₃N₄.
 31. The array of claim 27, wherein said grooves formed in said substrate are “V”-shaped grooves, formed by a bottom surface and angled sidewalls.
 32. The array of claim 27, wherein said antireflective coating layer is silicon dioxide.
 33. A photodiode array comprising: a substrate having at least a front side, a back side, and a handle wafer bonded to said front side; a plurality of photodiodes integrally formed in the substrate forming said array; and a plurality of electrical contacts in electrical communication with said front side, wherein front surface cathode and anode contacts are brought to a top surface of said handle wafer via metallization of channels.
 34. The array of claim 33, wherein said channels are formed from side walls of said handle wafer.
 35. The array of claim 34, wherein said channels connect a p+ metal pad to the p+ region and an n+ metal pad to the n+ region.
 36. The array of claim 34, wherein said side walls of said handle wafer comprise a first layer and a second layer.
 37. The array of claim 36, wherein said first layer comprises an oxide.
 38. The array of claim 36, wherein said second layer is boron doped polysilicon.
 39. The array of claim 36, wherein said second layer is phosphorus doped polysilicon.
 40. The array of claim 36, wherein said second layer is a p+ metal pad.
 41. The array of claim 36, wherein said second layer is an n+ metal pad.
 42. A photodiode array comprising: a substrate having at least a front side, a back side, and a handle wafer bonded to said front side; a plurality of photodiodes integrally formed in the substrate forming said array; a buried oxide layer formed between said substrate and said handle wafer; and a plurality of trenches operating as isolation trenches to nonconductively isolate electrically active regions.
 43. The array of claim 42, wherein said trench is defined by a doped trench sidewall, a trench sidewall liner, and a polysilicon filler.
 44. The array of claim 43, wherein said trench is further defined by a polysilicon step.
 45. The array of claim 42, wherein the trench sidewall liner is an oxide.
 46. The array of claim 42, wherein said doped trench sidewall is of n-type doping. 